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Data Sheet, Rev. 1.3, October 2007
SPOC - BTS5590G
SPI Power Controller
Automotive Power
SPOC - BTS5590G
Table of Contents
1 2 2.1 3 3.1 3.2 4 4.1 5 5.1 5.2 5.3 5.4 6 6.1 6.2 6.3 6.4 6.5 7 7.1 7.2 7.3 7.4 7.5 7.6 7.7 7.8 8 8.1 8.2 8.3 8.4 8.5 9 9.1 9.2 9.3 9.4 10 10.1 10.2 10.3 10.4 10.5 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Terms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Pin Assignment SPOC - BTS5590G . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Pin Definitions and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Supply Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Command Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Stages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Output ON-State Resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Input Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Stage Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Command Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Protection Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Over Load Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Over Temperature Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Reverse Polarity Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Over Voltage Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Loss of Ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Loss of Vbb . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Command Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Diagnosis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Diagnosis Word at SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Load Current Sense Diagnosis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Switch Bypass Diagnosis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Command Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Limp Home . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Trigger State Machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Command Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Serial Peripheral Interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SPI Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Daisy Chain Capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SPI Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 13 13 14 15 16 17 17 17 18 19 21 22 22 23 23 23 23 23 24 25 26 27 27 29 30 32 33 33 34 35 36 37 37 38 38 39 41
Data Sheet
Rev. 1.3, 2007-10-30
SPOC - BTS5590G
10.6 11 12 13
Register Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Application Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Package Outlines SPOC - BTS5590G . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Data Sheet
3
Rev. 1.3, 2007-10-30
SPI Power Controller for Advanced Light Control with Integrated LED Mode and Watchdog
SPOC - BTS5590G
1
Overview
The SPOC - BTS5590G is a five channel high-side smart power switch in PG-DSO-36-34 package providing embedded protective functions. It is especially designed to control standard exterior lighting in automotive applications. In order to use the same hardware with bulbs and LEDs, the device can be configured to bulb or LED mode. As a result, both load types are handeled optimized in switching and diagnosis accuracy. It is designed to drive lamps up to 3*27W + 2*10W. Configuration and status diagnosis is done via SPI. Additionally, there is a current sense signal available for each channel that is routed via a multiplexer to a single diagnosis pin.
PG-DSO-36-34
The SPOC - BTS5590G provides a fail-safe function with integrated watchdog. The watchdog is served via SPI by a sophisticated state machine providing secure limp home functionality. Product Summary Operating Voltage Power Switch Logic Supply Voltage Over Voltage Protection Maximum Stand-By Current at 25 C On-State Resistance at Tj = 150 channel 0, 1 channel 2 channel 3,4
VBB VDD VBB(AZ,min) IBB(OFF) RDS(ON) max
4.5 ... 28 V 3.8 ... 5.5 V 40 V 3 A 50 m 80 m 200 m
SPI Access Frequency
fSCLK(max)
1 MHz
Type SPOC - BTS5590G Data Sheet
Package PG-DSO-36-34 4
Marking BTS5590G Rev. 1.3, 2007-10-30
SPOC - BTS5590G
Overview Basic Features * * * * * * * * * 8 bit serial peripheral interface (daisy chain capable SPI) for control and diagnostics CMOS compatible parallel input pins for each channel provide straightforward PWM operation Selectable AND- / OR-combination for parallel inputs (PWM control) Very low stand-by current Optimized electromagnetic compatibility (EMC) for bulbs as well as LEDs Stable behavior at under voltage Device ground independent from load ground Green Product (RoHS-Compliant) AEC Qualified
Protective Functions * * * * * * * * Reverse battery protection with external components Short circuit protection Over load protection Multi step current limitation Thermal shutdown with latch Over voltage protection Loss of ground protection Electrostatic discharge protection (ESD)
Diagnostic Functions * * * * * * * Multiplexed proportional load current sense signals (IS) Enable function for current sense signal configurable via SPI High accuracy of current sense signal at wide load current range Current sense ratio (kILIS) configurable for LEDs or bulbs Very fast diagnosis in LED mode (<2% duty cycle at 100 Hz) Feedback on over temperature and over load via SPI Multiplexed switch bypass monitor provides short circuit to Vbb detection
Application Specific Functions * * * * Integration of adjustable watchdog timer with external capacitor Sophisticated trigger state machine with two bit increment and lock, served via SPI Fail-safe configuration via input pins Load type configuration via SPI (bulbs or LEDs) for optimized load control
Applications * * * High-side power switch for 12 V grounded loads in automotive application Especially designed for standard exterior lighting like tail light, brake light, reverse light, parking light, license plate lighting, turn signal indicators and equivalent LEDs Replaces electromechanical relays, fuses and discrete circuits
Data Sheet
5
Rev. 1.3, 2007-10-30
SPOC - BTS5590G
Overview
fail safe system
activation activation
watchdog
limp home
limp home
watchdog
SPOC - BTS5590G
200m 80m 50m 50m 200m
SPOC - BTS5590G
200m 50m 50m 80m 200m
BL IND TL
RL
LIC
SPOC
RL
BL IND TL
ApplicationWDrear .emf
Figure 1
Application Example
Abbreviations: BL RL TL LIC IND Brake Light (21 W, 27 W) Reverse Light (21 W, 27 W) Tail Light (5 W, 7 W, 10 W) License plate lighting (5 W, 10 W) Indicator / Flasher (21 W, 27 W)
Data Sheet
6
Rev. 1.3, 2007-10-30
SPOC - BTS5590G
Block Diagram
2
Block Diagram
The SPOC - BTS5590G is a five channel high-side power switch in PG-DSO-36-34 package providing embedded protective functions. There is a watchdog integrated with two bit increment trigger. An 8 bit serial peripheral interface (SPI) is used for configuration and diagnosis. The SPI can be used in daisy chain configuration. The sophisticated watchdog function provides secure limp home in combination with a limp home out signal. This signal can be individually connected to every input pin. The device provides a current sense signal per channel that is multiplexed to the diagnosis pin IS. It can be enabled and disabled via SPI commands. An over load and over temperature flag is provided in the SPI diagnosis word. A multiplexed switch bypass monitor provides diagnosis at short-circuit to VBB. The power transistors are built by N-channel vertical power MOSFETs with charge pumps. The device is monolithically integrated in SMART SIPMOS technology.
VBB
power supply driver logic
temperature sensor gate control & charge pump load current sense
clamp for inductive load
IN0 IN1 IN2 IN3 IN4
load current limitation
channel 0 1
OUT4
4 23
OUT3 OUT2 OUT1 OUT0
IS
ESD protection
current sense multiplexer PWM control
switch bypass monitor LED mode control limp home trigger state machine
VDD CS SCLK SO SI
watch dog ESD protection LHEN LHO LHD
SPI
GND
Figure 2
Block Diagram SPOC - BTS5590G
Data Sheet
7
Rev. 1.3, 2007-10-30
SPOC - BTS5590G
Block Diagram
2.1
Terms
The following figure shows all terms used in this data sheet.
Vbb IIN 0 VIN 0 VIN 1 VIN 2 VIN 3 VIN 4 Vdd VSO VSI VC S VSC LK VIS VLH EN VLH D VLH O IIN 1 IIN 2 IIN 3 IIN 4 ID D ISO I SI IC S ISC LK I IS ILH EN ILH D ILH O IBB VBB IN0 IN1 IN2 IN3 IN4 VDD SO SI CS SCLK IS LHEN LHD LHO GND IGN D OUT3 OUT2 I L2 VD S2 VOU T2 I L3 VD S3 VOU T3 OUT4 I L4 VD S4 VOU T4 OUT0 I L0 VD S0 VOU T0 OUT1 I L1 VD S1 VOU T1
TermsWD.emf
Figure 3
Terms
In all tables of electrical characteristics is valid: Channel related symbols without channel number are valid for each channel separately (e.g. VDS specification is valid for VDS0 ... VDS4). All SPI register bits are marked as follows: ADDR.PARAMETER (e.g. HWCR.CTL). In SPI register description, the values in bold letters (e.g. 0) are default values.
Data Sheet
8
Rev. 1.3, 2007-10-30
SPOC - BTS5590G
Pin Configuration
3
3.1
Pin Configuration
Pin Assignment SPOC - BTS5590G
(top view)
VBB GND VDD SO SI SCLK CS IN0 IN1 IN2 IN3 IN4 IS LHEN LHD LHO n.c. VBB
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18
36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19
VBB OUT0 OUT0 OUT0 OUT0 OUT1 OUT1 OUT1 OUT1 OUT2 OUT2 OUT2 OUT2 OUT3 OUT3 OUT4 OUT4 VBB
Figure 4
Pin Configuration PG-DSO-36-34
Data Sheet
9
Rev. 1.3, 2007-10-30
SPOC - BTS5590G
Pin Configuration
3.2
Pin
Pin Definitions and Functions
Symbol VBB VDD GND IN0 IN1 IN2 IN3 IN4 OUT0 OUT1 OUT2 OUT3 OUT4 CS SCLK SI SO IS LHEN LHD LHO n.c. I/O Function - - - I I I I I O O O O O I I I O O I O - Positive power supply for high-side power switch and limp home block Logic supply (5 V) Ground connection Input signal of channel 0 Input signal of channel 1 Input signal of channel 2 Input signal of channel 3 Input signal of channel 4 Protected high-side power output of channel 0 Protected high-side power output of channel 1 Protected high-side power output of channel 2 Protected high-side power output of channel 3 Protected high-side power output of channel 4 Chip select of SPI interface (low active) Serial clock of SPI interface Serial input of SPI interface Serial output of SPI interface Diagnosis output signal WD and LH Enable signal Limp Home output not connected, floating
Power Supply Pins 1, 18, 19, 36 1) 3 2 Parallel Input Pins 8 9 10 11 12 Power Output Pins 32, 33, 34, 35 2) 28, 29,30, 31 24, 25,26, 27 22, 23
2) 2) 2)
20, 21 2) SPI & Diagnosis Pins 7 6 5 4 13 Limp Home Pins 14 15 16 Other Pins 17
I/O Connection for external time base of watchdog
1) All VBB pins have to be connected. 2) All output pins of each channel have to be connected.
Data Sheet
10
Rev. 1.3, 2007-10-30
SPOC - BTS5590G
Electrical Characteristics
4
4.1
Electrical Characteristics
Absolute Maximum Ratings
Absolute Maximum Ratings1) Tj = -40 C to +150 C; all voltages with respect to ground, positive current flowing into pin. (unless otherwise specified). Pos. Parameter Symbol Limit Values min. Supply Voltage 4.1.1 4.1.2 4.1.3 4.1.4 Power supply voltage Logic supply voltage Reverse polarity voltage according Figure 26
VBB VDD
Unit
Conditions
max. 28 5.5 16 20 V V V V - -
TjStart = 25 C t 2 min 2)
-0.3 -0.3 - 0
-VBAT(rev)
Supply voltage for full short circuit protection (single VBB(SC) pulse) (Tj(0) = -40 C ... 150 C)
RECU = 20m RCable=
16m/m l = 0 or 5m 3)
LCable= 1H/m
4.1.5 4.1.6 4.1.7 4.1.8 4.1.9
Voltage at power transistor Supply Voltage for Load Dump protection Current through ground pin Current through VDD pin Load current
VDS VBB(LD) IGND IDD IL IIS VIN IIN
- - -100 -25
-IL(LIM)
54 41 25 12
IL(LIM)
V V mA mA A mA V mA
-
RI = 2 4) t = 400ms t 2 min t 2 min
5)
Power Stages Diagnosis Pin 4.1.10 Current through sense pin IS Input Pins 4.1.11 Voltage at input pins 4.1.12 Current through input pins SPI Pins 4.1.13 Voltage at chip select pin 4.1.14 Current through chip select pin 4.1.15 Voltage at serial input pin 4.1.16 Current through serial input pin 4.1.17 Voltage at serial clock pin 4.1.18 Current through serial clock pin 4.1.19 Current through serial output pin SO Limp Home Pins 4.1.20 Voltage at limp home enable pin 4.1.21 Current through limp home enable pin 4.1.22 Current through limp home output pin Data Sheet 11
VLHEN ILHEN ILHO VCS ICS VSI ISI VSCLK ISCLK ISO
-10 -0.3 -0.75 -2.0 -0.3 -2.0 -0.3 -2.0 -0.3 -2.0 -2.0 -0.3 -0.75 -2.0 -2.0
10 8.0 0.75 2.0 5.7 2.0 5.7 2.0 5.7 2.0 2.0 8.0 0.75 2.0 2.0
t 2 min
- - t 2 min -
t 2 min
V mA V mA V mA mA V mA mA
-
t 2 min
-
t 2 min t 2 min
- - t 2 min
t 2 min
Rev. 1.3, 2007-10-30
SPOC - BTS5590G
Electrical Characteristics Absolute Maximum Ratings1) Tj = -40 C to +150 C; all voltages with respect to ground, positive current flowing into pin. (unless otherwise specified). Pos. Parameter Symbol
VLHD ILHD Tj Tj TSTG VESD
Limit Values min. max. 5.7 1.0 150 60 150 -0.3 -1.0 -40 - -55
Unit V mA C K C kV
Conditions -
t 2 min
4.1.23 Voltage at limp home delay pin 4.1.24 Current through limp home delay pin Temperatures 4.1.25 Junction temperature 4.1.26 Dynamic temperature increase while switching 4.1.27 Storage temperature ESD Susceptibility 4.1.28 ESD resistivity HBM OUT pins other pins
- - - HBM6) - -
-4 -2
4 2
1) Not subject to production test, specified by design. 2) Specified RthJA value is according to Jedec JESD51-2,-5,-7 at natural convection on FR4 2s2p board; The Product (Chip+Package) was simulated on a 76.2 x 114.3 x 1.5 mm board with 2 inner copper layers (2 x 70m Cu, 2 x 35m Cu). 3) In accordance to AEC Q100-012 and AEC Q101-006. 4) RI is the internal resistance of the load dump pulse generator. 5) Current limitation is a protection feature. Operation in current limitation is considered as "outside" normal operating range. Protection features are not designed for continuous repetitive operation. 6) ESD resistivity, HBM according to EIA/JESD 22-A 114B (1.5k, 100pF).
Note: Stresses above the ones listed here may cause permanent damage to the device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Note: Integrated protection functions are designed to prevent IC destruction under fault conditions described in the data sheet. Fault conditions are considered as "outside" normal operating range. Protection functions are not designed for continuous repetitive operation.
Data Sheet
12
Rev. 1.3, 2007-10-30
SPOC - BTS5590G
Power Supply
5
Power Supply
The SPOC - BTS5590G is supplied by two supply voltages VBB and VDD. The VBB supply line is used by the power switches and by an internal power supply for the limp home function. The limp home power supply is enabled by pin LHEN. As a result, the stand-by current is minimized only when limp home function is disabled. The VDD supply line is used by the SPI related circuitry and for driving the SO line. A capacitor between pins VDD and GND is recommended. There is a power-on reset function implemented for the VDD logic supply voltage. After start-up of the logic power supply, all SPI registers are reset to their default values. The SPI interface including daisy chain function is active as soon as VDD is provided in the specified range independent of VBB.
5.1
Power Supply Modes
The following table shows all possible power supply modes for VBB, VDD and the internal power supply that is enabled by pin LHEN. Power Supply Modes VBB VDD LHEN PROFET operating Watchdog active SPI (logic) Stand-by current Idle current Diagnosis
1) 2) 3) 4)
0V 0V 0V - - reset - - -
0V 0V 5V - - reset - - -
0V 5V 0V - - - - -
0V 5V 5V - - - - -
13.5 V 0V 0V - reset - -
13.5 V 0V 5V - - -
1)
13.5 V 5V 0V - -
3)
13.5 V 5V 5V 1) 2) - - 4)
reset
An active and unserved watchdog will cause limp home mode after overrun. SPI reset in limp home mode. When all channels are in OFF-state and all SPI registers are at default values. Current sense diagnosis not available in limp home mode.
To achieve stand-by mode, the limp home block must be disabled (LHEN = 0 V), all channels must be switched off and the thermal latches have to be cleared. As a result the stand-by current IBB(OFF) is valid as listed. In case of active VDD supply, the idle mode parameters are valid only, when additionally all SPI registers are at default values (see Section 10.6) e.g. after a reset command.
Data Sheet
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Rev. 1.3, 2007-10-30
SPOC - BTS5590G
Power Supply
5.2
Reset
There are several reset trigger implemented in the device. They reset the SPI registers to their default values. The power stages as well as the analog watchdog block are not affected by the reset signals. The first SPI transmission after any kind of reset contains at pin SO the read information from register OUT, and the transmission error bit TER is set. Power-On Reset The power-on reset is released, when VDD voltage level is higher than VDD(PO). The SPI interface can be accessed after wake up time tWU(PO). Reset Command There is a reset command available to reset all register bits of the register bank and the diagnosis registers. As soon as HWCR.RST = 1, a reset is triggered equivalent to power-on reset. The SPI interface can be accessed after transfer delay time tCS(td). Limp Home Mode In limp home mode, the SPI write-registers are reset. The SPI interface is operating normally, so the limp home register bits LHO and LHEN as well as the error flags can be read.
Data Sheet
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Rev. 1.3, 2007-10-30
SPOC - BTS5590G
Power Supply
5.3
Electrical Characteristics
Electrical Characteristics Power Supply Unless otherwise specified: VBB = 9 V to 16 V, VDD = 3.8 V to 5.5 V, Tj = -40 C to +150 C. typical values: VBB = 13.5 V, VDD = 4.3 V, Tj = 25 C. Pos. 5.3.1 5.3.2 5.3.3 5.3.4 Parameter Operating voltage power switch Operating voltage watchdog Operating voltage for Watchdog memory in case of undervoltage Stand-by current for whole device with loads Symbol Limit Values min. typ. - - - max. 28 28
1)
Unit V V
Test Conditions - - -
VDD = 0 V VLHEN = 0 V VIN = 0 V Tj = 25 C Tj 85 C 1) Tj = 150 C VDD = 5 V VLHEN = 0 V VIN = 0 V Tj = 25 C Tj 85 C 1) Tj = 150 C
VBB VBB(WD) VBB(WD
memory)
4.5 9 3
1)
VBB(WD V
) min
IBB(OFF)
- - - 1.2 - - 3 3 50
A
Idle current for whole device with loads IBB(idle)
A
- - - 5.3.5 5.3.6 5.3.7 5.3.8 5.3.9 Logic supply voltage Logic supply current Logic idle current Operating current for whole device Power-On reset threshold voltage
- - - - 45 15 10 - -
3 3 50 5.5 150 35 20 3.8 500 V A A mA V s
VDD IDD IDD(idle) IGND VDD(PO) tWU(PO)
3.8 - - - - -
-
VCS = 0 V fSCLK = 0 Hz VCS = Vdd fSCLK = 0 Hz fSCLK = 0 Hz
- -
5.3.10 Power-On wake up time
1) Not subject to production test, specified by design.
Note: Characteristics show the deviation of parameter at the given supply voltage and junction temperature. Typical values show the typical parameters expected from manufacturing at VBB = 13.5 V, VDD = 4.3 V and Tj = 25 C.
Data Sheet
15
Rev. 1.3, 2007-10-30
SPOC - BTS5590G
Power Supply
5.4
Command Description
HWCR Hardware Configuration Register
W/R read write 4 LHO RST 3 WDL WDL 2 SBM 0 1 PWM PWM 0 CTL CTL
Field LHO
Bits 4
Type Description r Limp Home Out 0 Normal operation 1 Device in reset due to limp home mode Reset Command 0 Normal operation 1 Execute reset command
RST
4
w
Data Sheet
16
Rev. 1.3, 2007-10-30
SPOC - BTS5590G
Power Stages
6
Power Stages
The high-side power stages are built by N-channel vertical power MOSFETs (DMOS) with charge pumps. There are five channels implemented in the device. Each channel can be switched on via an input pin or via SPI register OUT. Channels 0, 1 and 2 provide a load type configuration for bulbs or LEDs in register WDLR. The load type configuration is allowed to be changed in OFF-state only.
6.1
Output ON-State Resistance
The on-state resistance RDS(ON) depends on the supply voltage VBB as well as on the junction temperature Tj. Figure 5 shows those dependencies. The behavior in reverse polarity mode is described in Section 7.3.
Vbb = 13.5 V
250 200 RDS(ON) /m 150 100 50 0 -50 -25 channel 0, 1 (bulb) channel 0, 1 (LED) channel 2 (bulb) channel 2 (LED) channel 3, 4 250 RDS(ON) /m 200 150 100 50 0 25 50 75 100 125 150 T /C 0 5 10 15 Vbb /V 20 25 channel 0, 1 (bulb) channel 0, 1 (LED) channel 2 (bulb) channel 2 (LED) channel 3, 4
Tj = 25 C
Figure 5
Typical On-State Resistance
6.2
Input Circuit
There are two ways of using the input pins in combination with the OUT SPI register by programming the HWCR.PWM parameter. * * HWCR.PWM = 0: A channel is switched on either by the according OUT register bit or the input pin. HWCR.PWM = 1: A channel is switched on by the according OUT register bit only, when the input pin is high. In this configuration, a PWM signal can be given to the input pin and the channel is activated by the SPI register OUT.
Figure 6 shows the complete input switch matrix.
OUT4 IN0 IIN0 IN1 IIN1 IN2 IIN2 IN3 IIN3 IN4 IIN4 PWM
InputMatrix.emf OR OR OR OR
OUT3
OUT2
OUT1
OUT0
OR
&
Gate Driver 0
&
Gate Driver 1
&
Gate Driver 2
&
Gate Driver 3
&
Gate Driver 4
Figure 6
Input Switch Matrix
The current sink to ground at the input pins ensures that the input signal is low in case of an open input pin. The zener diode protects the input circuit against ESD pulses. Data Sheet 17 Rev. 1.3, 2007-10-30
SPOC - BTS5590G
Power Stages
6.3
Power Stage Output
The power stages are built to be used in high side configuration (Figure 7).
VBB V ON V bb
OUT GND V OUT
Output.emf
Figure 7
Power Stage Output
The power DMOS switches with a dedicated slope, which is optimized in terms of EMC emission.
IN tON tOFF t
VOUT
90% 70%
70%
30% 10%
dV / dtON
dV / dtOFF
30%
t
SwitchOn.emf
Figure 8
Switching a Load (resistive)
When switching off inductive loads with high-side switches, the voltage VOUT drops below ground potential, because the inductance intends to continue driving the current. To prevent destruction of the device, there is a voltage clamp mechanism implemented that limits that negative output voltage to a certain level (VON(CL) (6.4.3)). See Figure 7 for details. The maximum allowed load inductance is limited.
Data Sheet
18
Rev. 1.3, 2007-10-30
SPOC - BTS5590G
Power Stages
6.4
Electrical Characteristics
Electrical Characteristic Power Stages Unless otherwise specified: VBB = 9 V to 16 V, Tj = -40 C to +150 C. typical values: VBB = 13.5 V, Tj = 25 C. Pos. Parameter Output Characteristics 6.4.1 On-State resistance channel 0, 1 - - - - channel 2 - - - - channel 3, 4 6.4.2 Output voltage drop limitation at small load currents channel 0, 1, 2 channel 3, 4 6.4.3 Output clamp 6.4.4 Output leakage current per channel channel 0, 1 channel 2 channel 3, 4 6.4.5 Inverse current capability per channel channel 0, 1, 2 channel 3, 4
-IL(IC)
Symbol min.
Limit Values typ. max.
Unit Test Conditions
RDS(ON)
22.8 39 74 116 - 50 - 150
m WDLR.LEDn = 0 1) Tj = 25 C, IL = 2.6 A Tj = 150 C, IL = 2.6 A WDLR.LEDn = 1 1) Tj = 25 C, IL = 700 mA Tj = 150 C, IL = 700 mA WDLR.LEDn = 0 1) Tj = 25 C, IL = 2.6 A Tj = 150 C, IL = 2.6 A WDLR.LEDn = 1 1) Tj = 25 C, IL = 700 mA Tj = 150 C, IL = 700 mA
1)
31.5 62 91 204 81 157
- 80 - 240 - 200 mV
- -
Tj = 25 C, IL = 1 A Tj = 150 C, IL = 1 A
VDS(NL)
- - 35 35 47 - - 54
IL = 35 mA IL = 35 mA
VON(CL) IL(OFF)
40
V A
IL = 20 mA VIN = 0 V OUT.OUTn = 0 VLHEN = 0 V VLHEN = 5 V VLHEN = 0 V VLHEN = 5 V VLHEN = 0 V VLHEN = 5 V
- - - - - -
0.1 - 0.1 - 0.1 -
10 40 10 40 8 40 A
No influence on functionality of unaffected channels 1) - -
- -
2.5 1.0
- -
Data Sheet
19
Rev. 1.3, 2007-10-30
SPOC - BTS5590G
Power Stages Electrical Characteristic Power Stages Unless otherwise specified: VBB = 9 V to 16 V, Tj = -40 C to +150 C. typical values: VBB = 13.5 V, Tj = 25 C. Pos. Parameter Thermal Resistance 6.4.6 Junction to Case 6.4.7 Junction to Ambient, all channels active Input Characteristics 6.4.8 L-input level 6.4.9 H-input level 6.4.10 L-input current 6.4.11 H-input current Timings 6.4.12 Turn-on time to 90% VBB channel 0, 1, 2 Symbol min. Limit Values typ. - 40 max. 20 - K/W K/W
1) 1) 2)
Unit Test Conditions
RthJC RthJA
- -
VIN(L) VIN(H) IIN(L) IIN(H) tON
-0.3 2.6 3 10
- - 25 40
1.0 5.5 75 75
V V A A s
- -
VIN = 0.4 V VIN = 5 V VBB = 13.5 V
- -
- - - - - - - - - - - -
250 100 250 s 290 120 290 0.5 1.5 0.5 0.5 1.5 0.5
WDLR.LEDn = 0 RL = 6.8 WDLR.LEDn = 1 RL = 33
RL = 18 VBB = 13.5 V
channel 3, 4 6.4.13 Turn-off time to 10% VBB channel 0, 1, 2
-
tOFF
- -
WDLR.LEDn = 0 RL = 6.8 WDLR.LEDn = 1 RL = 33
RL = 18
channel 3, 4 6.4.14 Turn-on slew rate 30% to 70% VBB dV/ dtON channel 0, 1, 2
- 0.1 0.1
V/s VBB = 13.5 V WDLR.LEDn = 0 RL = 6.8 WDLR.LEDn = 1 RL = 33
RL = 18
channel 3, 4 6.4.15 Turn-off slew rate 70% to 30% VBB -dV/ dtOFF channel 0, 1, 2
0.1 0.1 0.1
V/s VBB = 13.5 V WDLR.LEDn = 0 RL = 6.8 WDLR.LEDn = 1 RL = 33
RL = 18
channel 3, 4
0.1
1) Not subject to production test, specified by design. 2) Specified RthJA value is according to Jedec JESD51-2,-5,-7 at natural convection on FR4 2s2p board; The Product (Chip+Package) was simulated on a 76.2 x 114.3 x 1.5 mm board with 2 inner copper layers (2 x 70m Cu, 2 x 35m Cu).
Data Sheet
20
Rev. 1.3, 2007-10-30
SPOC - BTS5590G
Power Stages
6.5
Command Description
OUT Output Configuration Registers
W/R read/write RB 0 5 0 4 OUT4 3 OUT3 2 OUT2 1 OUT1 0 OUT0
Field OUTn n = 4 to 0
Bits n
Type r/w
Description Set Output Mode for Channel n 0 Channel n is switched off 1 Channel n is switched on
WDLR Watchdog and LED Mode Configuration Register
W/R read write 4 WDC WDTR 3 2 LED2 LED2 1 LED1 LED1 0 LED0 LED0
Field LEDn n = 2 to 0
Bits n
Type rw
Description Set LED Mode for Channel n 0 Channel n is in bulb mode 1 Channel n is in LED mode
HWCR Hardware Configuration Register
W/R read write 4 LHO RST 3 WDL WDL 2 SBM 0 1 PWM PWM 0 CTL CTL
Field PWM
Bits 1
Type rw
Description PWM Configuration 0 Input signal OR-combined with according OUT register bit 1 Input signal AND-combined with according OUT register bit
Data Sheet
21
Rev. 1.3, 2007-10-30
SPOC - BTS5590G
Protection Functions
7
Protection Functions
The device provides embedded protective functions, which are designed to prevent IC destruction under fault conditions described in this data sheet. Fault conditions are considered as "outside" normal operating range. Protective functions are neither designed for continuous nor for repetitive operation.
7.1
Over Load Protection
The load current IL is limited by the device itself in case of over load or short circuit to ground. There are multiple steps of current limitation which are selected automatically depending on the voltage VDS across the power DMOS. Please note that the voltage at the OUT pin is VBB - VDS. Please refer to following figures for details.
IL 25 20 15 10 5 5 10 15 20 25 V DS
CurrentLimitation01L .emf
WDLR.LED = 0
WDLR.LED = 1
Figure 9
IL 25 20 15 10 5
Current Limitation Channels 0, 1 (minimum values)
WDLR.LED = 0
WDLR.LED = 1
5
10
15
20
25
V DS
CurrentLimitation2L .emf
Figure 10
IL 12 10 8 6 4 2
Current Limitation Channels 2 (minimum values)
5
10
15
20
25
V DS
CurrentLimitation34 .emf
Figure 11
Current Limitation Channels 3, 4 (minimum values)
Current limitation to the value IL(LIM) is realized by increasing the resistance of the output channel, which leads to rapid temperature rise inside.
Data Sheet
22
Rev. 1.3, 2007-10-30
SPOC - BTS5590G
Protection Functions
7.2
Over Temperature Protection
A temperature sensor for each channel causes an overheated channel to switch off latched to prevent destruction ( also even in case of VDD = 0V). All over temperature latches are cleared by SPI command HWCR.CTL = 1.
IN t IL IL(LIM)
t IIS t ERR CTL = 1 t
OverLoad.emf
Figure 12
Shut Down by Over Temperature
7.3
Reverse Polarity Protection
In reverse polarity mode, power dissipation is caused by the intrinsic body diode of each DMOS channel as well as each ESD diode of the logic pins. The reverse current through the channels has to be limited by the connected loads. The current trough the ground pin, sense pin IS, the logic power supply pin VDD, the SPI pins and the watchdog pins has to be limited as well (please refer to the maximum ratings listed on Page 11). Note: No other protection mechanism such as temperature protection or current limitation is active during reverse polarity.
7.4
Over Voltage Protection
In addition to the output clamp for inductive loads as described in Section 6.3, there is a clamp mechanism available for over voltage protection. The current through the ground connection has to be limited during over voltage. Please note that in case of over voltage the pin GND may have a high voltage offset to the module ground.
7.5
Loss of Ground
In case of complete loss of the device ground connections, but connected load ground, the SPOC - BTS5590G securely changes to or stays in off-state.
7.6
Loss of Vbb
In case of loss of Vbb connection in on-state, all inductance of the loads has to be demagnetized through the ground connection or through an additional path from VBB to ground. When a diode is used in the ground path for reverse polarity reasons, the ground connection is not available for demagnetization. Then for example, a resistor can be placed in parallel to the diode or a suppressor diode can be used between VBB and GND.
Data Sheet
23
Rev. 1.3, 2007-10-30
SPOC - BTS5590G
Protection Functions
7.7
Electrical Characteristics
Electrical Characteristics Protection Functions Unless otherwise specified: VBB = 9 V to 16 V, Tj = -40 C to +150 C typical values: VBB = 13.5 V, Tj = 25 C Pos. Parameter Over Load Protection 7.7.1 Load current limitation channel 0 channel 1 channel 2 channel 3 channel 4 7.7.2 Initial short circuit shut down time channel 0, 1 channel 2 channel 3, 4 Over Temperature Protection 7.7.3 Thermal shut down temperature 7.7.4 Thermal hysteresis Reverse Battery 7.7.5 Drain-Source diode voltage (VOUT > Vbb) channel 0, 1 channel 2 channel 3, 4 Over Voltage 7.7.6 Overvoltage protection Loss of GND protection 7.7.7 Output current while GND disconnected
-VDS(rev)
Symbol min.
Limit Values typ. max.
Unit Test Conditions
IL(LIM)
24 7 24 7 24 7 12 12 - - - - - - - - 550 500 400 350 400 1701) 7 481) 181) 481) 181) 481) 181) 271) 27
1)
A
VDS = 7 V
WDLR.LEDn = 0 WDLR.LEDn = 1 WDLR.LEDn = 0 WDLR.LEDn = 1 WDLR.LEDn = 0 WDLR.LEDn = 1 - - s
TjStart = 25 C 1)
tOFF(SC)
- - - - - - - - - - - -
WDLR.LEDn = 0 WDLR.LEDn = 1 WDLR.LEDn = 0 WDLR.LEDn = 1 - C K mV -
1)
Tj(SC)
Tj
150 -
Tj = 150 C IL = -2.5 A IL = -2.5 A IL = -1 A
- - -
600 620 600 47 -
- - - 54 1 V mA
VBB(AZ) IL(GND)
40 -
IBB = 4 mA
1)
1) Not subject to production test, specified by design.
Data Sheet
24
Rev. 1.3, 2007-10-30
SPOC - BTS5590G
Protection Functions
7.8
Command Description
HWCR Hardware Configuration Register
W/R read write 4 LHO RST 3 WDL WDL 2 SBM 0 1 PWM PWM 0 CTL CTL
Field CTL
Bits 0
Type Description rw Clear Thermal Latch 0 Thermal latches are untouched 1 Command: Clear all thermal latches
Data Sheet
25
Rev. 1.3, 2007-10-30
SPOC - BTS5590G
Diagnosis
8
Diagnosis
For diagnosis purpose, the SPOC - BTS5590G provides a current sense signal and the diagnosis word at SPI. There is a current sense multiplexer implemented that is controlled via SPI. The sense signal can also be disabled by SPI command. A switch bypass monitor allows to detect a short circuit between the output pin and the battery voltage. Please refer to Figure 13 for details.
VBB
IIS 0(LE D) IIS 0
latch gate control
OR
temperature sensor
T
LED0 load current sense latch ERR0
load current limitation
OUT4 OUT3 OUT2 OUT1 OUT0 channel 0
1
0
DCR.MUX
VBB VDS (S B ) HWCR. SBM
current sense multiplexer IS R IS
DiagnosisL.emf
Figure 13
Block Diagram: Diagnosis
For diagnosis feedback at different operation modes, please see following table. Table 1 Operation Modes 1) Input Level OUT.OUTn L/0 (OFF-state) Output Level VOUT GND GND Z
VBB
Operation Mode Normal Operation (OFF) Short Circuit to GND Over Temperature Short Circuit to VBB Open Load Normal Operation (ON) Current Limitation Short Circuit to GND Over Temperature Short Circuit to VBB Open Load
Current Sense IIS Z Z Z Z Z
IL / kILIS
Error Flag ERRn2) 0 0 0 0 0 0 1 1 1
3)
HWCR. SBM 1 1 x 0 x 0 x 1 x 0 0
Z H/1 (ON-state)
~VBB
< VBB ~GND Z
VBB VBB
Z Z Z < IL / kILIS Z
0 0
1) L = low level, H = high level, Z = high impedance, potential depends on leakage currents and external circuit x = undefined 2) The error flags are latched until they are transmitted in the standard diagnosis word via SPI 3) The over temperature flag is set latched and can be cleared by SPI command HWCR.CTL
Data Sheet
26
Rev. 1.3, 2007-10-30
SPOC - BTS5590G
Diagnosis
8.1
Diagnosis Word at SPI
The standard diagnosis at the SPI interface provides information about each channel. The error flags, an OR combination of the over temperature flags and the over load monitoring signals are provided in the SPI standard diagnosis bits ERRn. The over load monitoring signals are latched in the error flags and cleared each time the standard diagnosis is transmitted via SPI. In detail, they are cleared between the second and third raising edge of the SCLK signal. The over temperature flags, which cause an overheated channel to stay switched off, are latched directly at the gate control block. The latches are cleared by SPI command HWCR.CTL. Please note: The over temperature information is latched twice. When transmitting a clear thermal latch command (HWCR.CLT), the error flag is cleared during command transmission of the next SPI frame and ready for latching after the third raising edge of the SCLK signal. As a result, the first standard diagnosis information after a CTL command will indicate a failure mode at the previously affected channels although the thermal latches have been cleared already. In case of continuous over load, the error flags are set again immediately because of the over load monitoring signal. In case of high duty cyle (off state of output < toff-state_min) the VDS might not be equal to VDD during the off state of the power Mosfet. The over load monitoring signals might be set and latched in the error flags. See Application Note "Software Strategy for Diagnosis during PWM-Operation" for more details.
8.2
Load Current Sense Diagnosis
There is a current sense signal available at pin IS which provides a current proportional to the load current of one selected channel. The selection is done by a multiplexer which is configured via SPI. The current sense signal (ratio kILIS = IL / IS) is provided as long as no failure mode occurs. The ratio kILIS can be adjusted to the load type (LED or bulb) via SPI register WDLR for channels 0 to 2. Usually a resistor RIS is connected from the current sense pin to GND. It is recommended to use resistors 2.5 k 6000
5000
dummy bulb: Tj = 150C dummy bulb: Tj = -40C dummy led: Tj = 150C dummy led: Tj = -40C
4000 kILIS
3000
2000
1000
0
0.5
1
1.5
2
2.5
3 3.5 IL0,1 /A
4
4.5
5
5.5
6
Figure 14
Current Sense Ratio kILIS Channel 0,1 1)
1) The curves show the behavior based on characterization data. The marked points are guaranteed in this Data Sheet in Section 8.4 (Position 8.4.1).
Data Sheet
27
Rev. 1.3, 2007-10-30
SPOC - BTS5590G
Diagnosis
6000
5000
dummy bulb: Tj = 150C dummy bulb: Tj = -40C dummy led: Tj = 150C dummy led: Tj = -40C
4000 kILIS
3000
2000
1000
0
0.5
1
1.5
2 IL2 /A
2.5
3
3.5
4
Figure 15
Current Sense Ratio kILIS Channel 2 1)
3000
dummy Tj = 150C dummy Tj = -40C
2500
kILIS
2000
1500
1000
500 0 0.5 1 IL3,4 /A 1.5 2
Figure 16
Current Sense Ratio kILIS Channel 3, 4 1)
In case of over current as well as over temperature, the current sense signal of the affected channel is switched off. To distinguish between over temperature and over load, the SPI diagnosis word can be used. Whereas the over load flag is cleared every time the diagnosis is transmitted, the over temperature flag is cleared by a dedicated SPI command (HWCR.CTL). Details about timings between the current sense signal IIS and the output voltage VOUT and the load current IL can be found in Figure 17.
1) The curves show the behavior based on characterization data. The marked points are guaranteed in this Data Sheet in Section 8.4 (Position 8.4.1).
Data Sheet
28
Rev. 1.3, 2007-10-30
SPOC - BTS5590G
Diagnosis
IN
OFF
ON tON
OFF tOFF t
V OUT
t IL
IIS
ts IS (ON)
t sIS (LC)
t dIS (OFF)
t
t
SenseTiming.emf
Figure 17
Timing of Current Sense Signal
Current Sense Multiplexer There is a current sense multiplexer implemented in the SPOC - BTS5590G that routes the sense current of the selected channel to the diagnosis pin IS. The channel is selected via SPI register DCR.MUX. The sense current also can be disabled by SPI register DCR.MUX. For details on timing of the current sense multiplexer, please refer to Figure 18.
CS DCR.MUX 111 IIS
000 tsIS (E N)
001 ts IS (MUX )
111 t dIS (MUX ) t
t
MuxTiming.emf
Figure 18
Timing of Current Sense Multiplexer
8.3
Switch Bypass Diagnosis
To detect short circuit to VDD, there is a switch bypass monitor implemented. In case of short circuit between the output pin OUT and VBB in ON-state, the current will flow through the power transistor as well as through the short circuit (bypass) with undefined ratio. As a result, the current sense signal will show lower values than expected by the load current. In OFF-state, the output voltage will stay close to VBB potential which means a small VDS. The switch bypass monitor compares the voltage VDS across the power transistor of that channel which is selected by the current sense multiplexer (DCR.MUX) with threshold VDS(SB). The result of comparison can be read in SPI register HWCR.SBM. The switch bypass monitor is active in ON- as well as in OFF-state.
Data Sheet
29
Rev. 1.3, 2007-10-30
SPOC - BTS5590G
Diagnosis
8.4
Electrical Characteristics
Electrical Characteristics Diagnosis Unless otherwise specified: VBB = 9 V to 16 V, Tj = -40 C to +150 C typical values: VBB = 13.5 V, Tj = 25 C Pos. Parameter Load Current Sense 8.4.1 Current sense ratio channel 0, 1 (bulb):
IL = 1.3 A IL = 2.6 A IL = 6.0 A IL = 1.3 A IL = 2.6 A IL = 6.0 A kILIS
Symbol Limit Values min. typ. max.
Unit Test Conditions
2400 2400 2500 2450 2450 2700 400 600 650 750 500 650 700 800 2400 2400 2500 2450 2450 2700 400 600 650 750 500 650 700 800 550 650 700 700
3100 3000 3000 3030 3000 3000 1300 1100 1030 950 1250 1080 1000 965 3100 3000 3000 3000 3000 3000 1300 1100 1000 950 1250 1080 1000 965 975 925 875 875
3800 3500 3500 3600 3350 3300 2200 1600 1400 1150 2000 1500 1300 1130 3800 3500 3500 3600 3350 3300 2200 1600 1400 1150 2000 1500 1300 1130 1400 1200 1050 1050
WDLR.LEDn = 0 Tj = -40 C - -
Tj = 150 C - -
channel 0,1 (LED):
IL = 35 mA IL = 0.3 A IL = 0.7 A IL = 2.0 A IL = 35 mA IL = 0.3 A IL = 0.7 A IL = 2.0 A
WDLR.LEDn = 1 Tj = -40 C - - -
Tj = 150 C - - -
channel 2 (bulb):
IL = 1.3 A IL = 2.6 A IL = 3.5 A IL = 1.3 A IL = 2.6 A IL = 3.5 A
WDLR.LEDn = 0 Tj = -40 C - -
Tj = 150 C - -
channel 2 (LED):
IL = 35 mA IL = 0.3 A IL = 0.7 A IL = 1.3 A IL = 35 mA IL = 0.3 A IL = 0.7 A IL = 1.3 A
WDLR.LEDn = 1 Tj = -40 C - - -
Tj = 150 C - - - Tj = -40 C - - -
channel 3, 4:
IL = 0.3 A IL = 0.6 A IL = 1.3 A IL = 2.0 A
Data Sheet
30
Rev. 1.3, 2007-10-30
SPOC - BTS5590G
Diagnosis Electrical Characteristics Diagnosis Unless otherwise specified: VBB = 9 V to 16 V, Tj = -40 C to +150 C typical values: VBB = 13.5 V, Tj = 25 C Pos. Parameter
IL = 0.3 A IL = 0.6 A IL = 1.3 A IL = 2.0 A
Symbol Limit Values min. 600 680 720 720 typ. 950 890 875 875 max. 1300 1100 1030 1030 8% 2 1
Unit Test Conditions
Tj = 150 C - - -
8.4.2 Current sense voltage limitation 8.4.3 Current sense leakage / offset current
VIS(LIM) IIS(en)
-8% - -
Vdd
- -
V A A s
IIS = 1 mA
IL = 0 DCR.MUX = 000B
IL = IL(nom) DCR.MUX = 111B VBB = 13.5 V IL = IL(nom) RIS = 4.7 k WDLR.LEDn = 0
8.4.4 Current sense leakage, while diagnosis IIS(dis) disabled 8.4.5 Current sense settling time after channel activation
tsIS(ON)
- - - - 300 115
WDLR.LEDn = 1 s
VBB = 13.5 V 1) IL = IL(nom) RIS = 4.7 k WDLR.LEDn = 0
8.4.6 Current sense desettling time after channel deactivation
tdIS(OFF)
- - - - 25 25
WDLR.LEDn = 1 s
VBB = 13.5 V 1) RIS = 4.7 k WDLR.LEDn = 0 IL = 1.3 A to 2.6 A IL = 0.6 A to 1.3 A RIS = 4.7 k DCR.MUX:111B -> 000B RIS = 4.7 k DCR.MUX:000B -> 001B
1)
8.4.7 Current sense settling time after change tsIS(LC) of load current channel 0, 1, 2 channel 3, 4 8.4.8 Current sense settling time after current tsIS(EN) sense activation 8.4.9 Current sense settling time after multiplexer channel change 8.4.10 Current sense deactivation time 8.4.11 Off state time during PWM operation Switch Bypass Monitor 8.4.12 Switch bypass monitor threshold - - - - - 350 150 0.7 - - - - - - - - 30 30 25 30 25 - - 2.5
s s s s
tsIS(MUX) tdIS(MUX) toff
state_min
RIS = 4.7 k DCR.MUX: 001B -> 111B
WDLR.LEDn = 0 WDLR.LEDn = 1 -
VDS(SB)
V
1) Not subject to production test, specified by design.
Data Sheet
31
Rev. 1.3, 2007-10-30
SPOC - BTS5590G
Diagnosis
8.5
Command Description
DCR Diagnosis Control Registers
4 0 3 0 2 1 MUX 0
Field MUX
Bits 2:0
Type Description rw Set Current Sense Multiplexer Configuration 000 current sense of channel 0 is routed to IS pin 001 current sense of channel 1 is routed to IS pin 010 current sense of channel 2 is routed to IS pin 011 current sense of channel 3 is routed to IS pin 100 current sense of channel 4 is routed to IS pin 101 IS pin is high impedance 110 IS pin is high impedance 111 IS pin is high impedance
HWCR Hardware Configuration Register
W/R read write 4 LHO RST 3 WDL WDL 2 SBM 0 1 PWM PWM 0 CTL CTL
Field SBM
Bits 2
Type Description r Switch Bypass Monitor1) 0 VDS < VDS(SB) 1 VDS > VDS(SB)
1) Invalid in stand-by mode
Standard Diagnosis
CS TER 7 0 6 LHEN 5 WDL 4 ERR4 3 ERR3 2 ERR2 1 ERR1 0 ERR0
Field ERRn n = 4 to 0
Bits n
Type Description r Error flag Channel n 0 normal operation 1 failure mode occurred
Data Sheet
32
Rev. 1.3, 2007-10-30
SPOC - BTS5590G
Limp Home
9
Limp Home
The SPOC - BTS5590G provides a sophisticated watchdog function with trigger state machine to build a secure limp home signalling. The fail safe block is supplied via VBB and provides an output signal at pin LHO in case of watchdog overrun independently of VDD. There is an enable pin LHEN available which is usually connected to the ignition signal of the car. As soon as the limp home function is enabled, the watchdog is started and must be served. The timing can be adjusted in a wide range by choosing the appropriate capacitor. For calculation of the watchdog timing, please refer to Section 9.1. The watchdog is served via a trigger state machine, which starts at a defined state when limp home has been enabled. As a result, the state machine might also be reset to this startup state due to a voltage drop at pin LHEN. A watchdog overrun causes the LHO pin to turn from tri-state to a high signal. This signal can be utilized to switch on dedicated channels by connecting LHO to the appropriate input pins and it is suitable to turn other hardware of the system into limp home mode as well. Once the watchdog has been overrun, it can be reset by a low signal at pin LHEN only. There is no software reset mechanism implemented for this function to make sure, a faulty software can not turn off the limp home mode. The status of the watchdog as well as the trigger state machine can be read via SPI. As a result, the micro controller can perform a watchdog check via SPI. Please see following Figure 19 for details.
VBB LHEN power supply VLHD(O) ILHD(C) ILHD(D) sub WDC += 1
OR OR
trigger state machine LHEN LHO WDL WDTR WDC & &
1 0
LHO LHD CWD V LHD(R)
GND
LimpHome .emf
Figure 19
Block Diagram: Limp Home
9.1
Watchdog
The watchdog function is built as analog trigger watchdog with external capacitor CWD as time base. A high signal at pin LHEN enables the watchdog. A constant current loads the external capacitor, so the voltage rise is linear. When the watchdog is served, the capacitor is discharged to level VLHD(R) and the cycle starts again. Please see following figure for details.
LHEN trigger VLHD WDTR == WDC t t V LHD(O) VLHD(R) WDC += 1 VLHO t
Watchdog.emf
t
Figure 20 Data Sheet
Watchdog Behavior 33 Rev. 1.3, 2007-10-30
SPOC - BTS5590G
Limp Home The limp home out signal (LHO) is generated, when the voltage at pin LHD exceeds threshold VLHD(O). In this case, all SPI registers are reset, but the read-only parameters (LHO, ERRn) are still available. The SPI interface including daisy chain capability is not affected by this reset signal. As a result it can be accessed normally. The maximum watchdog serve time which is the minimum watchdog overrun time tWD(O,min) is calculated by following formula:
C WD(min) ( V LHD(O,min) - V LHD(R,max) ) t WD(O,min) = ------------------------------------------------------------------------------------------------I LHD(C,max)
(1) The maximum watchdog overrun time tWD(O,max) is calculated by following formula:
C WD(max) ( V LHD(O,max) - V LHD(R,min) ) t WD(O,max) = -------------------------------------------------------------------------------------------------I LHD(C,min)
(2)
There is an under voltage reset implemented in the watchdog block. In case of VBB lower than the operating voltage range of the watchdog (Position 5.3.2, Vbb(WD)), the LHO driver is deactivated and the external capacitor CWD is discharged. As soon as the voltage rises above the under voltage threshold, the capacitor is charged again and the LHO driver is activated. In case of fast VBB transients between VBB(WD memory)min and VBB(WD) min voltage and VLHD > VLHD(R) the watchdog capacitor CWD is only discharged as long as the voltage is below VBB(WD) min. I.e. in case of very short transients the charging or discharging process will continue after the disturbance with the same mode (charging or discharging) as before the voltage break down as long as VLHD > VLHD(R).
9.2
Trigger State Machine
A trigger state machine is implemented to ensure secure limp home signalling.
LHO 1
V LH
WDC 0
D
V LHD VLHD(R)
TR D W
WDC 1
< >W DC
LH EN (L )
W DC
W DL =0
=V
<>
LH EN
LHEN 0
VLHEN = V LHEN(H)
WDC 3
VLHD V LHD(R)
W DT R
V
V LHEN = V LHEN(L)
<> DC W
V LHD VLHD(R)
W DT R
WDL 1
W DL = R DT W <> DC W
0
V
D LH ) (O
=0 DL W
V LHD V LHD(R)
=0 DL W
WDC 2
TriggerSM .emf
Figure 21
Trigger State Machine
There are two bits in the SPI register block (WDLR.WDTR) that have to be subsequently increased to serve the watchdog. The WDLR.WDC parameter is increased by the device itself as soon as the capacitor is discharged below threshold VLHD(R). The watchdog lock (HWCR.WDL) is set, when an incorrect WDLR.WDTR value (WDLR.WDTR <> WDLR.WDC) has been written via SPI. To serve the watchdog then, the lock bit has to be cleared and the correct WDLR.WDTR value (WDLR.WDTR = WDLR.WDC) has to be written. The HWCR.WDL bit is also part of the standard diagnosis (WDL) and can be monitored at each SPI access. The lock of the state machine trigger ensures that only correct handling will serve the watchdog. Any incorrect WDLR.WDTR value will lock the trigger for the watchdog, which will overrun after the specified timings.
Data Sheet
34
Rev. 1.3, 2007-10-30
SPOC - BTS5590G
Limp Home The trigger state machine is reset to the default values (see Section 10.6) by the following events: * * * Pin LHEN = low Pin LHO = 1 (limp home mode) The reset sources described in Section 5.2
9.3
Electrical Characteristics
Electrical Characteristics Limp Home Unless otherwise specified: VBB = 9 V to 16 V, Tj = -40 C to +150 C, VLHEN = 5 V. typical values: VBB = 13.5 V, Tj = 25 C. Pos. Parameter Limp Home 9.3.1 H-output voltage level of pin LHO 9.3.2 Current limitation of pin LHO Watchdog 9.3.3 Charge current for CWD 9.3.4 Discharge current for CWD 9.3.5 Overrun threshold voltage at pin LHD 9.3.6 Recharge threshold voltage at pin LHD Input Characteristics 9.3.7 L-input level at pin LHEN 9.3.8 H-input level at pin LHEN 9.3.9 L-input current through pin LHEN 9.3.10 H-input current through pin LHEN
VLHEN(L) VLHEN(H) ILHEN(L) ILHEN(H) ILHD(C) -ILHD(D) VLHD(O) VLHD(R) VLHO(H) ILHO(lim)
Symbol
Limit Values min. 5 2 15 300 4.0 0.4 -0.3 2.6 3 7 typ. - - 22 - 4.4 0.5 - - - 30 max. 9 - 30 - 4.8 0.6 1.0 5.5 85 85
Unit Test Conditions
V mA A A V V V V A A
VLHD = 5 V ILHO = 1 mA VLHD = 5 V
- - - - - -
VLHEN = 0.4 V VLHEN = 5 V
Data Sheet
35
Rev. 1.3, 2007-10-30
SPOC - BTS5590G
Limp Home
9.4
Command Description
WDLR Watchdog and LED Mode Configuration Register
W/R read write 4 WDC WDTR 3 2 LED2 LED2 1 LED1 LED1 0 LED0 LED0
Field WDC WDTR
Bits 4:3 4:3
Type r w
Description Watchdog trigger state machine counter (default value 11) Watchdog trigger register (default value 00)
HWCR Hardware Configuration Register
W/R read write 4 LHO RST 3 WDL WDL 2 SBM 0 1 PWM PWM 0 CTL CTL
Field LHO
Bits 4
Type Description r Limp Home Out 0 Device is in normal operation mode 1 Device is in limp home mode Watchdog Lock 0 Watchdog can be served 1 Watchdog state machine trigger is locked
WDL
3
rw
Standard Diagnosis
CS TER 7 0 6 LHEN 5 WDL 4 ERR4 3 ERR3 2 ERR2 1 ERR1 0 ERR0
Field LHEN
Bits 6
Type r
Description Limp Home Enable 0 L-input signal at pin LHEN 1 H-input signal at pin LHEN Watchdog Lock 0 Watchdog can be served 1 Watchdog trigger state machine is locked
WDL
5
r
Data Sheet
36
Rev. 1.3, 2007-10-30
SPOC - BTS5590G
Serial Peripheral Interface (SPI)
10
Serial Peripheral Interface (SPI)
The serial peripheral interface (SPI) is a full duplex synchronous serial slave interface, which uses four lines: SO, SI, SCLK and CS. Data is transferred by the lines SI and SO at the rate given by SCLK. The falling edge of CS indicates the beginning of an access. Data is sampled in on line SI at the falling edge of SCLK and shifted out on line SO at the rising edge of SCLK. Each access must be terminated by a rising edge of CS. A modulo 8 counter ensures that data is taken only, when a multiple of 8 bit has been transferred. The interface provides daisy chain capability.
SO SI CS SCLK
time
SPI.emf CS MSB MSB 6 6 5 5 4 4 3 3 2 2 1 1 LSB LSB
Figure 22
Serial Peripheral Interface
10.1
SPI Signal Description
CS - Chip Select: The system micro controller selects the SPOC - BTS5590G by means of the CS pin. Whenever the pin is in low state, data transfer can take place. When CS is in high state, any signals at the SCLK and SI pins are ignored and SO is forced into a high impedance state. CS High to Low transition: * * The requested information is transferred into the shift register. SO changes from high impedance state to high or low state depending on the logic OR combination between the transmission error flag (TER) and the signal level at pin SI. As a result, even in daisy chain configuration, a high signal indicates a faulty transmission. This information stays available to the first rising edge of SCLK.
CS Low to High transition: * Command decoding is only done, when after the falling edge of CS exactly a multiple (1, 2, 3, ...) of eight SCLK signals have been detected. In case of faulty transmission, the transmission error flag (TER) is set and the command is ignored. Data from shift register is transferred into the addressed register.
*
SCLK - Serial Clock: This input pin clocks the internal shift register. The serial input (SI) transfers data into the shift register on the falling edge of SCLK while the serial output (SO) shifts diagnostic information out on the rising edge of the serial clock. It is essential that the SCLK pin is in low state whenever chip select CS makes any transition. SI - Serial Input: Serial input data bits are shifted-in at this pin, the most significant bit first. SI information is read on the falling edge of SCLK. The input data consists of two parts, control bits followed by data bits. Please refer to Section 10.5 for further information. SO Serial Output: Data is shifted out serially at this pin, the most significant bit first. SO is in high impedance state until the CS pin goes to low state. New data will appear at the SO pin following the rising edge of SCLK. Please refer to Section 10.5 for further information. Data Sheet 37 Rev. 1.3, 2007-10-30
SPOC - BTS5590G
Serial Peripheral Interface (SPI)
10.2
Daisy Chain Capability
The SPI of SPOC - BTS5590G provides daisy chain capability. In this configuration several devices are activated by the same CS signal MCS. The SI line of one device is connected with the SO line of another device (see Figure 23), in order to build a chain. The ends of the chain are connected with the output and input of the master device, MO and MI respectively. The master device provides the master clock MCLK which is connected to the SCLK line of each device in the chain.
device 1
MO SI SPI SO SI
device 2
SPI SO SI
device 3
SPI SO
CS
CS
SCLK
SCLK
CS
MI MCS MCLK
Figure 23
Daisy Chain Configuration
In the SPI block of each device, there is one shift register where one bit from SI line is shifted in each SCLK. The bit shifted out occures at the SO pin. After eight SCLK cycles, the data transfer for one device has been finished. In single chip configuration, the CS line must turn high to make the device accept the transferred data. In daisy chain configuration, the data shifted out at device 1 has been shifted in to device 2. When using three devices in daisy chain, three times eight bits have to be shifted through the devices. After that, the MCS line must turn high (see Figure 24).
MI MO MCS MCLK
time
SPI_DasyChain2.emf
SO device 3 SI device 3
SO device 2 SI device 2
SO device 1 SI device 1
Figure 24
Data Transfer in Daisy Chain Configuration
10.3
Timing Diagrams
tCS(lead) tCS(lag) tSCLK(P) tSCLK(H) tSCLK(L)
0.7Vdd 0.2Vdd
tCS(td)
0.7Vdd 0.2Vdd
CS
SCLK
tSI(su) tSI(h)
SI
tSO(en) tSO(v) tSO(dis)
0.7Vdd 0.2Vdd
SO
0.7Vdd 0.2Vdd SPI Timing.emf
Figure 25
Timing Diagram SPI Access
Data Sheet
38
SCLK
SPI_DasyChain.emf
Rev. 1.3, 2007-10-30
SPOC - BTS5590G
Serial Peripheral Interface (SPI)
10.4
Electrical Characteristics
Electrical Characteristics SPI Unless otherwise specified: Vbb = 9 V to 16 V, Tj = -40 C to +150 C, Vdd = 3.8 V to 5.5 V typical values: Vbb = 13.5 V, Tj = 25 C, Vdd = 4.3 V Pos. Parameter Symbol Limit Values min. Input Characteristics (CS, SCLK, SI) 10.4.1 L level of pin CS VCS(L) SCLK VSCLK(L) SI VSI(L) 10.4.2 H level of pin CS VCS(H) SCLK VSCLK(H) SI VSI(H) 10.4.3 L-input pull-up current at CS pin 10.4.4 H-input pull-up current at CS pin
ICS(L) ICS(H)
Unit Test Conditions
typ.
max. V
VDD = 4.3 V - - - VDD = 4.3 V - - - VDD = 4.3 V,VCS = 0 V VDD = 4.3 V,VCS = 2.6 V VDD = 4.3 V VSCLK = 0.4 V VSI = 0.4 V VDD = 4.3 V VSCLK = 4.3 V VSI = 4.3 V ISO = -0.5 mA ISO = 0.5 mA,VDD = 4.3 V VCS =VDD
-0.3 -0.3 -0.3 2.6 2.6 2.6 10 3 3 3 10 10 0
VDD 0.5 V
- - - - - - 30 - - - 30 30 - - - - - - - - - - - - -
1.0 1.0 1.0 V 5.5 5.5 5.5 85 85 75 75 A 75 75 0.5
VDD
A A A
10.4.5 L-input pull-down current at pin SCLK ISCLK(L) SI ISI(L) 10.4.6 H-input pull-down current at pin SCLK ISCLK(H) SI ISI(H) Output Characteristics (SO) 10.4.7 L level output voltage 10.4.8 H level output voltage 10.4.9 Output tristate leakage current Timings 10.4.10 Serial clock freqency 10.4.11 Serial clock period 10.4.12 Serial clock high time 10.4.13 Serial clock low time
fSCLK tSCLK(P) tSCLK(H) tSCLK(L) VSO(L) VSO(H) ISO(OFF)
V V A
-10 0 1 500 500 1 1 2 100 100 -
10 1 - - - - - - - - 1
MHz - s ns ns s s s ns ns s - - - - - - - -
CL = 20 pF 1)
10.4.14 Enable lead time (falling CS to rising tCS(lead) SCLK) 10.4.15 Enable lag time (falling SCLK to rising CS) 10.4.16 Transfer delay time (rising CS to falling CS)
tCS(lag) tCS(td)
10.4.17 Data setup time (required time SI to tSI(su) falling SCLK) 10.4.18 Data hold time (falling SCLK to SI)
tSI(h)
10.4.19 Output enable time (falling CS to SO tSO(en) valid)
Data Sheet
39
Rev. 1.3, 2007-10-30
SPOC - BTS5590G
Serial Peripheral Interface (SPI) Electrical Characteristics SPI Unless otherwise specified: Vbb = 9 V to 16 V, Tj = -40 C to +150 C, Vdd = 3.8 V to 5.5 V typical values: Vbb = 13.5 V, Tj = 25 C, Vdd = 4.3 V Pos. Parameter Symbol - - Limit Values min. 10.4.20 Output disable time (rising CS to SO tSO(dis) tri-state) 10.4.21 Output data valid time with capacitive load
tSO(v)
Unit Test Conditions 1 s ns
CL = 20 pF 1) CL = 20 pF 1)
typ. - -
max.
500
1) Not subject to production test, specified by design.
Data Sheet
40
Rev. 1.3, 2007-10-30
SPOC - BTS5590G
Serial Peripheral Interface (SPI)
10.5
SPI Protocol
CS1) 7 Write Register 1 Read Register 0 0 TER TER 0 1 x LHEN ADDR 6 ADDR ADDR x WDL x x ERR4 x x ERR3 5 4 3 2 DATA x x ERR2 DATA x x ERR1 0 1 ERR0 1 0
SI SI SI SO SO
Read Standard Diagnosis Standard Diagnosis Second Frame of Read Command
1) The SO pin shows this information between CS hi -> lo and first SCLK lo -> hi transition.
Note: Reading a register needs two SPI frames. In the first frame the RD command is sent. In the second frame the output at SPI signal SO will contain the requested information. A new command can be executed in the second frame.
Field TER
Bits CS
Type Description r Transmission Error 0 Previous transmission was successful (modulo 8 clocks received) 1 Previous transmission failed or first transmission after reset Address Pointer to register for read and write command Data Data written to or read from register selected by address ADDR Limp Home Enable 0 L-input signal at pin LHEN 1 H-input signal at pin LHEN Watchdog Lock 0 Watchdog can be served 1 Watchdog trigger state machine is locked Diagnosis of Channel x 0 No failure 1 Over temperature, over load or short circuit
ADDR DATA LHEN
6:5 4:0 6
rw rw r
WDL
5
r
ERRx x = 4 to 0
x
r
Data Sheet
41
Rev. 1.3, 2007-10-30
SPOC - BTS5590G
Serial Peripheral Interface (SPI)
10.6
Name OUT WDLR HWCR DCR
Register Overview
W/R W/R R W R W W/R Addr 00B 01B 01B 10B 10B 11B LHO RST 0 4 OUT4 WDC WDTR WDL WDL 0
2)
3 OUT3
2 OUT2 LED2 LED2 SBM 0
1 OUT1 LED1 LED1 PWM PWM MUX
0 OUT0 LED0 LED0 CTL CTL
default1) 00H 18H 00H 00H 00H 07H
1) The default values are set after reset. 2) Can be cleared only via SPI. The bit is set by internal signals.
Data Sheet
42
Rev. 1.3, 2007-10-30
SPOC - BTS5590G
Application Description
11
Application Description
Vbat
5V
500 100nF
68nF
VDD VCC GPIO GPIO
LHO 8k 8k
VBB
IN0 IN1 IN2 IN3 IN4 IS OUT0 OUT1 OUT2 OUT3 GND
3.3k
27W 27W 27W 10W 10W
C
AD
1k 1nF
OUT4
VDD SPI
2k
VBB Limp Home LHEN LHO LHD
470nF 2k
Ignition
20k
CS SCLK SO SI GND
SPI
2k 2k 2k
LHO
10k
VSS
10k
Schottky
10nF.. 100nF
CircuitWD .emf
Figure 26
Application Circuit Example
Data Sheet
43
Rev. 1.3, 2007-10-30
SPOC - BTS5590G
Package Outlines SPOC - BTS5590G
12
Package Outlines SPOC - BTS5590G
2.65 MAX.
0.35 x 45 7.6 -0.2
0.23 +0.09
1)
0.2 -0.1
2.45 -0.2
0.65 0.33 0.08
2)
0.1
C
0.70.2 10.3 0.3
0.17 M C A-B D 36x
D
A
36 19
Bottom View
19 36
Ejector Mark
1 18 18 1
B 1) 12.8 -0.2
Index Marking Index Marking
1) Does not include plastic or metal protrusion of 0.15 max. per side 2) Does not include dambar protrusion of 0.05 max. per side
GPS01089
Figure 27
PG-DSO-36-34 (Plastic Dual Small Outline Package)
Green Product (RoHS compliant) To meet the world-wide customer requirements for environmentally friendly products and to be compliant with government regulations the device is available as a green product. Green products are RoHS-Compliant (i.e Pb-free finish on leads and suitable for Pb-free soldering according to IPC/JEDEC J-STD-020).
You can find all of our packages, sorts of packing and others in our Infineon Internet Page "Products": http://www.infineon.com/products.
8 MAX.
Dimensions in mm
Data Sheet
44
Rev. 1.3, 2007-10-30
SPOC - BTS5590G
Revision History
13
Revision 1.3 1.2
Revision History
Date 07-10-30 07-08-28 Changes * * * * Chapter 7.1 Current limitation curves channels 0, 1 added Chapter 11 Package outline drawing changed 4.1 Conditions updated 4.1 and 6.4 : footnote change to : Specified RthJA value is according to Jedec JESD512,-5,-7 at natural convection on FR4 2s2p board; The Product (Chip+Package) was simulated on a 76.2 x 114.3 x 1.5 mm board with 2 inner copper layers (2 x 70m Cu, 2 x 35m Cu).
* * * * * 1.1 07-03-05 * * * *
4.1.4 Conditions updated 4.1.28 Definition change 5.2 Reset Command : tCS(td) change to : tCS(td). 8.4.3 New parameter : Current sense leakage / offset current Max Input Voltage value change to 40 Volts Product summary Green Product (ROHS compliant) and AEC Qualified added 4.1.12 Current through input pins min value change to -0.75mA 4.1.21 Current through limp home enable pin min value change to -0.75mA Chapter9.1 In case of fast VBB transients between VBB(WD memory)min and VBB(WD) min voltage and VLHD > VLHD(R) the watchdog capacitor CWD is only discharged as long as the voltage is below VBB(WD) min. I.e. in case of very short transients the charging or discharging process will continue after the disturbance with the same mode (charging or discharging) as before the voltage break down as long as VLHD > VLHD(R). Chapter 5.3 New parameter defined : VBB(WD memory) Chapter 6 Ron definition changed Chapter 9.2 DCR change to WDLR Chapter 7.2 (also even in case of Vdd = 0V) added. Basic Feature : Green Logo added Chapter 8.1 In case of high duty cyle ( off state of output < toff state_min) the VDS might not be equal to VBB during the off state of the power Mosfet. The over load monitoring signals might be set and latched in the error flags. See Application Note " Software Strategy for Diagnosis during PWM-Operation" for more details Table 8.4.10 Off stateTime during PWM operation definition Chapter 11 68nF added between VBB and Gnd page 18: register read value added New template DIN A4 V1.2
* * * * * *
* * * *
Data Sheet
45
Rev. 1.3, 2007-10-30
Edition 2007-10-30 Published by Infineon Technologies AG 81726 Munich, Germany (c) 2007 Infineon Technologies AG All Rights Reserved. Legal Disclaimer The information given in this document shall in no event be regarded as a guarantee of conditions or characteristics. With respect to any examples or hints given herein, any typical values stated herein and/or any information regarding the application of the device, Infineon Technologies hereby disclaims any and all warranties and liabilities of any kind, including without limitation, warranties of non-infringement of intellectual property rights of any third party. Information For further information on technology, delivery terms and conditions and prices, please contact the nearest Infineon Technologies Office (www.infineon.com). Warnings Due to technical requirements, components may contain dangerous substances. For information on the types in question, please contact the nearest Infineon Technologies Office. Infineon Technologies components may be used in life-support devices or systems only with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered.

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